Cypress instrument cluster solution enables Yazaki graphics
Cypress Semiconductor Corp. announced that automotive supplier Yazaki North America has implemented Cypress’ instrument cluster solution to drive the advanced graphics in its instrument cluster for an American car manufacturer. The Cypress solution is based on a Traveo microcontroller (MCU), along with two high-bandwidth HyperBus memories in a multi-chip package (MCP), an analog power management IC (PMIC) for safe electrical operation, and a PSoC MCU for system management support.
“Our customer wanted an instrument cluster with rich graphics that would enhance the user experience for drivers and help differentiate their high-end crossover and truck models,” said Spencer Weidig, Senior Program Manager at Yazaki. “Working with a single, devoted supplier such as Cypress for multiple core components allowed for a cost-effective system solution and simplified the design process for this instrument cluster, which has been well received. The solution’s scalability helped us address three different vehicle levels efficiently.”
Sven Natus, Senior Director of the Automotive Business Unit at Cypress, said, “We take a long-term view of our collaboration with automotive suppliers such as Yazaki, offering them tailored solutions based on our broad portfolio of Traveo microcontrollers and leveraging our best-in-class fail-safe storage and data-logging, power management ICs, and other technologies for added convenience.”
Cypress says its Traveo devices in the Yazaki instrument cluster were the industry’s first 3D-capable Arm Cortex-R5 cluster MCUs, and they are designed to provide greater memory savings, increased safety features, and rich image capabilities. The MCU works seamlessly with Cypress’ HyperBus MCP device, which combines a high-speed, 512-Mbit NOR Flash device for fast-boot, instant-on capability, and a 64-Mbit self-refresh DRAM for expanded scratchpad memory. The MCP is meant to enable bandwidth-intensive processing with low latency, and its low pin count is intended to simplify designs compared to complex double data rate (DDR) memories.