Building efficient onboard chargers for electric vehicles using SiC cascodes
The increasing uptake of electric vehicles (EVs) is good news for the planet but challenging news for the electricity grid, which will have to cope with both increased demand and the need to charge all sorts of badly behaved loads.
Why badly behaved? Because switched-mode power supplies (SMPSs), as used in EV battery chargers, draw current from the AC power grid out of phase with the supply voltage. In an SMPS, the AC line input is rectified and then the resultant, rather choppy DC power is smoothed out using bulk capacitors topped up with charge at the peak of the AC cycle. This means that the load presented to the power grid is non-linear, taking current in such short bursts that it can distort the supply’s sinusoidal line voltage, flattening its peak as shown in Figure 1.
The resultant current waveform has an in-phase component at line frequency, and a reactive component, 90 degrees out of phase with the line, which has multiple harmonics, of differing amplitudes, caused by the non-linear nature of the SMPS as a load. This creates an issue for EV charger designers, because standards such as EN 61000-3-2 define limits to the harmonic current emissions that a load is allowed to produce.
Using power factor correction to reduce harmonics
The most common way to cut the current distortion caused by an SMPS is to pass the rectified line voltage through a boost converter that outputs a regulated DC voltage greater than the peak of the line AC (Figure 2). A sensor keeps track of the line current, and pulse-width modulation is applied to the boost converter to keep the current in phase with the line voltage. This reduces harmonic currents and so improves the supply’s power factor, i.e. the ease with which it can be driven by the AC line supply.
The combination of bridge rectifier and boost converter shown in Figure 2 has been used for power factor correction (PFC) for many years, but now limits overall system efficiency because the subsequent converter stages are already about 97% efficient.
In operation, two of the diodes in the bridge are always conducting and each have around a 1 V drop across it so that, for example, at least 18 W is dissipated in the bridge of a 1k W, 115 V-input converter. This reduces its efficiency by two percent, reducing system efficiency to 95%. With standards requiring complete converters to exceed 96% efficiency at high line and half load, this is a problem.
A better solution is to use the main switching device to also act as a synchronous rectifier, with its channel arranged to conduct from source to drain only. This bridgeless totem-pole circuit is shown at left in Figure 3. D5 is replaced with a similar switch to Q1, so both Q1 and Q2 now act as boost switch and synchronous rectifier, swapping their function on alternate mains polarities. This topology means that only one diode and the source-drain resistance of a switch is in series with the current, considerably reducing conduction losses.
For further efficiency gains, the diodes D 1 and D2 can be replaced with synchronous switches, as shown at right in Figure 3.
Challenges and (partial) solutions
There is no such thing as a free lunch, and so there are still issues to be overcome with using a bridgeless totem-pole circuit to improve power factors. These include the need for special current-monitoring and AC zero-crossing detection circuits, as well as issues with soft starting. It’s also vital that switches Q1 and Q2 always have a dead time when neither conducts, to avoid catastrophic “shoot-through” currents. During this dead time, the inherent body diodes of the Q1 or Q2 MOSFETs, acting as rectifiers, conduct the full output current. When the device is reverse-biased in the next phase of the switching cycle, a large reverse-recovery current flows, and this causes power dissipation and EMI problems that reduce the efficiency gains made elsewhere.
High-voltage MOSFETs can have particularly poor reverse-recovery characteristics, which has limited the use of bridgeless totem-pole circuits at higher powers.
This is changing with the availability of wide bandgap SiC MOSFETs with low channel-conduction losses, high switching speeds, and fast body diodes. However, the forward voltage of the diode can be 2.5 V – 3 V, causing high conduction losses. The energy stored in the device’s capacitance can also be twice that of a silicon MOSFET, causing greater switching losses.
The SiC cascode option
One way around these issues is to use SiC cascodes, formed by packaging a high-voltage SiC JFET with a high-performance, low-voltage Si-MOSFET. The resultant device has low switching losses, due in part to its extremely low input, output, and Miller capacitances and its low energy-storage figure made possible by a small die size. SiC cascodes offer drain-source resistance per unit area figures that are about 10 times lower than silicon super-junction MOSFETs, and two to four times lower than SiC MOSFETs.
The Si-MOSFET in the SiC cascode introduces a body diode, but its low-voltage nature means it is fast and so has a low reverse-recovery current and loss. Figure 4 compares the recovery characteristics of a 650V UnitedSiC UJC06505T SiC cascode and a 650 V IPP65R045C7 silicon super-junction MOSFET, showing about 60 times less recovered charge in the SIC device.
A demo board from UnitedSiC, rated at 1.5 kW and using UJC06505K SiC cascodes running at 100 kHz, shows that the required efficiency targets are easily met (Figure 5).
The use of bridgeless totem-pole circuits for PFC has been limited by the lack of an appropriate switching technology. The availability of SiC cascode switches now makes it possible to benefit from the efficiency improvements promised by the topology. The devices’ ruggedness also makes them a good practical choice.